Unfolding Method for Shabal on Virtex-5 FPGAs: Concrete ResultsPosted on July 28th, 2010 No comments
In this paper, we focus on an optimized implementation of the Shabal candidate. We improve the state-of-the-art using the unfolding method. This transformation leads to unroll a part of the Shabal core. More precisely, our design can produce a throughput over 3 Gbps on Virtex-5 FPGAs, with a reasonable area usage.
Authors: Julien Francq and Céline Thuillet
Note: This work was partially supported by the French Agence Nationale de la Recherche through the SAPHIR2 project under Contract ANR-08-VERS-014.