A submission to NIST's Cryptographic Hash Algorithm Competition
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  • Optimized implementations of Shabal

    Posted on October 4th, 2010 Jeff No comments

    The optimized C implementation of Shabal provides a performance of about 7.5 cpb on an Intel Core2 processor in 64-bit mode, but only 9.3 cpb in 32-bit mode. We present here an implementation in assembly for i386, which achieves 7.5 cpb on an Intel Core2. This implementation is also quite shorter than the compiled C code (4813 bytes, including 2.8 kB for precomputed initial values for all 16 supported output sizes) and compatible with the complete i386 processor family.

    We also include two optimized assembly implementations for x86 processor with SSE2 instructions, in 32-bit and 64-bit mode. Shabal was not designed to take advantage of vector instruction sets such as SSE2. But a moderate usage of these instruction can nonetheless help speed up the implementation of Shabal. Achieved bandwidth is around 5.9 cpb in both 32-bit and 64-bit mode. SSE2 instructions are available on all Intel processors from the Pentium 4 onward, and are a standard part of the 64-bit ABI.

    Download: Optimized implementations of Shabal (1220)

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